The present invention relates to a MOS memory employing insulated-gate field effect transistors (hereinbelow, termed "MOS transistors"), and more particularly to a one-transistor type dynamic random access memory. D.RAMs employing MOS transistors have been quadrupled in scale every 3 years since a dynamic random access memory (hereinbelow, abbreviated to "d.RAM") of 1 kb was sold early in the 1970s. However, 16-pin DIPs (dual in-line packages) have been chiefly used as packages for receiving memory chips, and the sizes of cavities for putting the chips therein have been limited, so that the memory chips have been enlarged only to at most 1.4 times with the quadrupling of the scale. Accordingly, the memory cell area corresponding to 1 bit has decreased significantly with the enlargement of scale. Specifically it has been reduced to about 1/3 with the quadrupling of the scale. The capacitance C of a memory capacitor is expressed by C=.epsilon.A/t (where .epsilon.: dielectric constant of an insulator film, A: area of the capacitor, t: thickness of the insulator film). Therefore, when the area A becomes 1/3, the capacitance C becomes 1/3 as long as the quantities .DELTA. and t remain unchanged. The quantity of a signal S as the memory capacitor is proportional to the quantity of charges Q, which is the product between the capacitance C and a voltage V. Therefore, as the area A decreases, the quantity of charges Q diminishes proportionally, and the signal S consequently becomes small.
Letting N denote noise, the S/N ratio lowers with the decrease of the signal S, which forms a serious problem during circuit operation. Accordingly, the decrement of the area A has been usually compensated for by the decrement of the thickness t. As the scale has been enlarged to 4 kb, 16 kb and 64 kb, the thickness of a typical SiO.sub.2 film has been thinned to 100 nm, 75 nm and 50 nm by way of example.
Further, it has recently been verified that charges of about 200 fC at the maximum are generated within a Si substrate by .alpha. particles emitted from radioactive metals (U, Th etc.) contained in a package etc. and that they form noise. Because of this it has become difficult to obtain high reliability operation that the quantity of charges representing the quantity of a signal is rendered to a value less than approximately 200 fC.
It has accordingly been practised to thin the insulator film still more. For this reason, the dielectric breakdown of the insulator film has become a problem. The dielectric breakdown electric field of SiO.sub.2 is at most 10.sup.7 V/cm. Accordingly, an SiO.sub.2 film being 10 nm thick is almost permanently broken down or is degraded by the application of 10 V. In addition, when the long-term reliability is considered, it is important to use an insulator film with a voltage which is smaller than the maximum breakdown voltage to the utmost.
FIG. 1 shows an arrangement diagram of the memory cell of a one-transistor type d.RAM. The memory cell is constructed of a capacitor 1 for storing charges, and a switching MOS transistor 2. The drain of the switching transistor is connected to a bit line 3, and the gate thereof to a word line 4.
The memory cell is operated in such a way that the signal charges stored in the capacitor 1 are read out by the switching transistor 2. In order to construct an actual memory of N bits, a memory array is arranged. Herein, broadly there are two methods to be described below. FIG. 2 shows the so-called "open bit line" arrangement in which bit lines 31 and 32 are arrayed on both the sides of a sense amplifier 5 for differentially deriving a signal. In this arrangement, only one bit line 31 electrically intersects one word line 41, and the difference of the signals of the bit lines 31 and 32 is detected by the sense amplifier 5.
FIG. 3 shows the other arrangement called the "folded bit lline" arrangement. Two bit lines 31 and 32 connected to a sense amplifier 5 are arrayed in parallel, and one word line 41 intersects the two bit lines 31 and 32.
While the embodiments of the present invention to be described later will chiefly refer to the folded bit line arrangement, the invention is similarly applicable to the open bit line arrangement.
When, as indicated in FIGS. 2 and 3, C.sub.D denotes the capacitance of the parasitic capacitor 6 of the bit line 32 and C.sub.S denotes the capacitance of the capacitor 12 of a memory cell, one of the principal performance indices of this memory array becomes C.sub.S /C.sub.D. The S/N ratio of this memory array is in 1-to-1 correspondence with C.sub.S /C.sub.D. Not only increasing the capacitance of the capacitor of the memory cell, but also decreasing the parasitic capacitance C.sub.D of the bit line 32 results in enhancing the S/N ratio similarly.
FIG. 4 shows an example of the plane of the memory cell of the folded bit line system. A part of an active region (isolated region) 7 surrounded with a thick field oxide film for isolation, which is usually thicker than 100 nm, is covered with a plate 8 in order to form a capacitor. The plate is selectively removed from a portion 40 which includes a part for forming a switching transistor and a contact hole 9 for connecting a bit line electrode to a drain on a Si substrate. In this portion, word lines 41 and 42 are deposited, and the switching transistor 2 is formed. In order to facilitate understanding, FIG. 5 shows a sectional view of a part indicated by AA in FIG. 4.
Hereinafter, for the sake of convenience, transistors shall be exemplified as being of the n-channel type. In order to fabricate p-channel type transistors, the conductivity types of a Si substrate and diffused layers may, in general, be reversed to those in the case of the n-channel type.
On a p-type Si substrate 10 of approximately 10 .OMEGA.-cm, a field SiO.sub.2 film 11 which is usually approximately 100-1000 nm thick is selectively formed by, e.g., the so-called LOCOS process which employs Si.sub.3 N.sub.4 for an oxidation impermeable mask. Thereafter, a gate oxide film 12 which is 10-100 nm thick is formed on the Si substrate 10 by the thermal oxidation process or the like. Subsequently, a capacitor electrode 25 made of an n.sup.+ -type layer is formed by the selective doping of P or As. Subsequently, the plate 8 which is represented by polycrystalline Si doped with P or As is selectively deposited, and the plate 8 of the polycrystalline Si is oxidized to form a first inter-layer oxide film 13. Thereafter, a word line 4 which is typically made of polycrystalline Si, Mo silicide or a refractory metal (Mo or W) is deposited, and the ions of P, As or the like are implanted. Then, in those parts of the active region on which the plate 8 and the word line 4 are not deposited, n.sup.+ -type diffused layers 15 are formed to serve as the source and drain of the switching transistor 2. Subsequently, PSG 14 which contains phosphorus and which is produced by the so-called CVD process is deposited by 500-1000 nm, the contact hole 9 is formed in a place where a bit line 3 represented by an Al electrode is to be connected to the diffused layer 15, and the bit line 3 is selectively deposited.
In this memory cell, the region 16 of the capacitor 1 to serve as the memory capacitor is a part indicated by oblique lines in FIG. 4. When the memory cell itself becomes small, also the part of the region 16 becomes small. As explained before, unless the gate oxide film 12 is thinned, the capacitor capacitance C.sub.S lowers, which is seriously problematic in the memory operation.
To the end of solving such problems, it has been proposed to form a recess in a semiconductor substrate and to utilize the recess for a capacitor (Japanese Patent Publication No. 56-48976, Japanese Patent Application Laying-Open No. 51-130178, and Japanese Patent Application Laying-Open No. 58-154256).